Logic devices such as FPGAs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of large systems often requires the use of EDA tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) flow are synthesis, mapping, placement, and routing.
Typically during synthesis, a designer inputs a description of the system into the EDA tool. Traditionally, the description of the system includes a register transfer level (RTL) description to describe the operation of synchronous digital circuits. In RTL design, a circuit's behavior is defined in terms of the flow of signals between hardware registers and the logical operations performed on those signals. RTL abstraction is used in hardware description languages such as Verilog and very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) to create high-level representations of a circuit, from which lower-level representations and can be derived.
In the past, the RTL description provided to the EDA tool from the designer would include the appropriate delay elements to support appropriate timing on a specified target device. Thus, when creating the RTL description, familiarity with the characteristics of the architecture of the target device and the specification of resources of the target device would be required by the designer since the RTL description would vary depending on these attributes. RTL descriptions would also be required from a designer to manage data paths that required external control. Typically a separate RTL block would be created to perform address decode. The RTL block would be manually connected which would require additional time and effort from the designer.